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General Information

Job Title
Senior FV Engineering Manager
Job ID
7926
Country
India
City
Bangalore
Date Posted
21-Nov-2024
Job Category
Engineering
Job Subcategory
R&D Engineering
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned verification professional with a passion for leading and mentoring teams. You possess a deep understanding of formal verification methodologies and have a proven track record in managing complex verification projects. Your excellent interpersonal and communication skills enable you to effectively collaborate with cross-functional teams and drive projects to successful completion. You are proactive in identifying and addressing verification challenges and are always on the lookout for innovative ways to enhance verification efficiency and coverage. With your extensive experience in digital design and verification, you are well-versed in high-speed interconnect protocols and industry-standard formal verification tools.

What You’ll Be Doing:

  • Lead, mentor, and grow a team of formal verification engineers, providing technical guidance, career development, and performance management to ensure a high-performing and engaged team.
  • Develop and drive the formal verification plans, aligning with project timelines and IP deliverables. Define test plans tailored to high-complexity digital IPs, including CXL, UCIe, USB, and other interconnect protocols.
  • Manage multiple verification projects concurrently, coordinating with design, RTL, and DV teams. Ensure verification goals, timelines, and milestones are met while maintaining quality standards.
  • Identify and implement state-of-the-art formal verification methodologies and tools, including assertions, SystemVerilog Assertions (SVA), and custom verification environments. Drive innovation to enhance verification efficiency and coverage.
  • Evaluate and mitigate verification risks early in the design phase, ensuring that IPs meet high-quality standards and are thoroughly verified before release.
  • Collaborate with senior management on matters concerning several functional areas, divisions, and/or customers to drive verification strategies and ensure alignment with broader business objectives.

The Impact You Will Have:

  • Ensure the successful verification of complex digital IPs, contributing to the delivery of high-quality products to our customers.
  • Enhance the efficiency and coverage of verification processes through the implementation of innovative methodologies and tools.
  • Build and maintain a high-performing verification team through effective leadership, mentorship, and career development.
  • Drive the alignment of verification plans with project timelines and IP deliverables, ensuring timely and successful project completion.
  • Mitigate verification risks early in the design phase, reducing the likelihood of costly design errors and rework.
  • Collaborate with cross-functional teams to ensure a cohesive and integrated approach to verification, design, and development.

What You’ll Need:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Advanced degrees preferred.
  • X+ years of experience in formal verification of digital design IPs, with a strong track record in verifying complex IPs.
  • Proven experience in managing and leading teams, with excellent interpersonal and communication skills.
  • Deep understanding of formal verification methodologies, including property-based and equivalence checking, SystemVerilog Assertions (SVA), and protocol compliance.
  • Strong familiarity with industry-standard formal verification tools, such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal.
  • Extensive experience in digital design and verification for high-speed interconnect protocols.
  • Excellent problem-solving abilities and a proactive approach to identifying and addressing verification challenges.

Who You Are:

  • A natural leader who inspires and motivates their team to achieve excellence.
  • An excellent communicator who can effectively convey complex technical concepts to diverse audiences.
  • A proactive problem solver who takes initiative to address challenges and implement solutions.
  • A collaborative team player who works well with cross-functional teams to achieve common goals.
  • An innovative thinker who continuously seeks to improve processes and methodologies.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and motivated team of formal verification engineers. Our team is dedicated to ensuring the highest quality standards for digital IPs through rigorous verification processes. We are committed to continuous learning and innovation, leveraging the latest tools and methodologies to stay at the forefront of the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.