Synopsys

Position: ASIC Digital Design Engineer (RTL/DV/Synthesis)

Location: 

• Tan Binh Ward, Ho Chi Minh city
• Hanoi
• Danang

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

What You'll Be Doing:

You will be in charge one of these following jobs of ASIC Digital Design Engineering

RTL Design Engineering

• Accountable to develop document and writing RTL for sub blocks that are part of the IP product.
• Checking, report and fix issue of RTL by Lint tool.
• Join with Verification team to work on the product's verification tasks.
• Participate in on-job training program from seniors.

Design Verification Engineering

• Work in a Digital and Verification Development team during the development and validation of complex digital mix signals for high-speed interface IP.
• Writing test cases, checkers, and coverage that implement the verification test plan.
• Functional and Coverage report
• Debug of simulations
• Complete all design quality checks and data quality checks

Synthesis Engineering

• Doing Logical Synthesis, understanding of digital P&R, Formal Verification.
• Analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.
• Work closely with design engineer to ensure netlist quality.
• Complete all design quality checks and data quality checks

What You'll Need:

General Requirements:

• Bachelor's or Master's degree in Electronics - Electrical Engineering, or Telecommunications; Computer Science Engineering or related ones.
• 1-2 year working experience in similar roles.
• Fresh graduates are also welcomed and offered the on-the-job training to adapt the position's requirements)
• Fresh graduates with prior internship or research experience in any semiconductor company or IC design lab is a plus
• Being trained in any training course or program related to IC Design is a plus
• Good command of English (4 skills)
• Self-learning skills
• A self-motivated and highly responsible
• A good team player, willing to support other

Technical Requirements:

• Have knowledge about digital hardware components (AND, OR, XOR, NOT, latches, flipflop, etc.).
  
• Have knowledge about Boolean algebra.
• Have knowledge about Analog Mixed Signal is a plus.
• Familiar with tools: VCS, Verdi, Spyglass or similar tools is a plus.
• Experience in scripting languages including Perl, TCL, Python is a plus.
• Familiar with Verilog is a big plus.
• Familiar with Synopsys synthesis tools is preferred.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.