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General Information

Job Title
ASIC Digital Design, Manager
Job ID
6251
Country
Taiwan
City
Hsinchu
Date Posted
11-Sep-2024
Job Category
Engineering
Job Subcategory
ASIC Digital Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

Manager, ASIC Digital Design

We're looking for a Manager, ASIC Digital Design, focusing on verification, to join the team.

The candidate would be working as part of a highly experienced DDR/LPDDR/HBM controller design and verification team, targeting the current and next generation DDR technology, such as HBM4, DDR5, LPDDR6. Solid theoretical and practical background in AXI, CHI, CRYPTO and RAS is a solid plus.

The position offers an excellent opportunity to work with a professional team responsible for delivering high-end designs from specification development to performing functional verification, performance analysis down to successful IP releases.
The controller IP development is very dynamic and provides an endless list of challenges. This work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.
Does this sound like a good role for you?

Responsibilities
 

  • Provide strong leadership to engineers to ensure the exceptional quality.
  • Use SystemVerilog, UVM, C++ and scripting languages with industry-leading simulation tools and methodologies to verify complex designs.
  • Negotiate program objectives with Architecture, Design and Software teams. Lead the team through planning, architecting, defining strategy, documenting, execution, reviewing and closure of verification, and deliver on schedule and with good quality.
  • Make sure the team follow company’s rules of quality management.
  • Bring management skills to the team, support individual development and goal definition, whilst aligning team vision for outstanding results.
  • Collaborate effectively with multi-functional teams to tackle new challenges, using robust written and verbal abilities. 
  • Support customers from all over the world in queries for verification. 


Key Qualifications
 

  • Expert knowledge of verification languages and methodologies
  • Determines verification methods and procedures on new assignments and projects.
  • Frequently performs in project leadership role.
  • Fulfil DV ownership of verification complex IP at big partition level or Top-level
  • knowledge of DDR, LPDDR or HBM is preferred. 
  • Excellent planning, execution and communication skills, with strong ability to collaborate across sites and disciplines
  • Experienced in managing an engineering team, to achieve organisational objectives and align teams.


Preferred Experience
 

  • Typically requires a minimum of 8+ years of related experience.
  • At this level, post-graduate coursework or knowledge base equivalent may be desirable.



Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.