Synopsys

ASIC Digital Design, Manager-IP Verification

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking ASIC Digital Design, Manager-IP Verification professional, eager to lead and inspire a team dedicated to excellence in IP verification. Your expertise lies in architecting robust verification environments for complex serial protocols, leveraging HVL (System Verilog), and utilizing industry-standard simulators. You have a deep understanding of verification methodologies like VMM, OVM, and UVM, and are experienced with protocols such as MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB. Your proficiency with HDLs and scripting languages (Verilog, Perl, TCL, Python) enables you to streamline verification processes and drive innovation. You possess a meticulous attention to detail, outstanding problem-solving capabilities, and communicate clearly across diverse teams. Your leadership style fosters collaboration, motivates high performance, and encourages knowledge sharing within a global environment. You thrive in fast-paced settings, adapt quickly to changing priorities, and are passionate about developing the next generation of connectivity protocols for commercial, enterprise, and automotive applications. Your vision and initiative are key to elevating the quality and reliability of Synopsys’ IP cores, making a tangible impact on the industry.

What You’ll Be Doing:

• Specifying, designing, and implementing advanced verification environments for the DesignWare family of synthesizable cores.
• Overseeing verification tasks for IP cores, including comprehensive test planning and coding at unit and system levels.
• Developing and executing detailed test cases, debugging issues, coding for functional coverage, and ensuring rigorous testing to meet quality goals.
• Managing regression processes and ensuring strict adherence to industry-leading verification methodologies.
• Collaborating closely with RTL designers and a global team of verification engineers to drive seamless integration and innovation.
• Leading efforts on next-generation connectivity protocols tailored for commercial, enterprise, and automotive markets.

The Impact You Will Have:

• Enhance the reliability and performance of Synopsys’ IP cores through meticulous verification processes.
• Contribute to the creation and advancement of cutting-edge connectivity protocols, influencing industry standards.
• Drive innovation in chip design and verification, supporting the development of high-performance silicon solutions.
• Ensure delivery of high-quality, robust IP cores to customers, reinforcing Synopsys’ reputation for excellence.
• Promote continuous improvement of verification methodologies and best practices within the organization.
• Foster collaboration and knowledge sharing across global teams, elevating collective expertise and performance.

What You’ll Need:

• Bachelor’s degree in Electrical Engineering (BSEE) with 10+ years of relevant experience, or Master’s degree (MSEE) with 8+ years.
• Demonstrated experience architecting verification environments for complex serial protocols.
• Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.
• Expertise in verification methodologies including VMM, OVM, and UVM.
• Strong knowledge of protocols (MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB).
• Familiarity with Verilog and scripting languages (Perl, TCL, Python) for automation and process improvement.
• Experience with IP design, verification processes, and VIP development.

Who You Are:

• Detail-oriented and analytical, with exceptional problem-solving skills.
• Proactive and initiative-driven, able to anticipate challenges and opportunities.
• Excellent communicator, both written and verbal, across diverse and global teams.
• Collaborative team player, fostering a positive and inclusive work environment.
• Adaptable and resilient, capable of managing multiple tasks and shifting priorities effectively.

The Team You’ll Be A Part Of:

You will join the DesignWare IP Verification R&D team at Synopsys, a dynamic and innovative group dedicated to specifying, designing, and implementing verification environments for synthesizable cores. Working alongside RTL designers, you’ll collaborate with a global team of professional verification engineers focused on developing next-generation connectivity protocols for diverse applications across commercial, enterprise, and automotive sectors.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.