Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a passion for digital design and verification, eager to make a lasting impact in advanced semiconductor technology. With over a decade of hands-on experience, you bring technical mastery and strategic vision to every project. You thrive in dynamic environments, seamlessly balancing architectural planning with hands-on execution. Your expertise spans RTL development, mixed-signal IPs, and advanced verification methodologies, making you a go-to authority for complex challenges.

You are a collaborative leader who enjoys mentoring junior engineers and establishing verification standards. Your communication skills bridge cross-functional teams, ensuring smooth project delivery across global locations. You continuously seek new tools and techniques to enhance efficiency and innovation, and you are adept at navigating multi-disciplinary projects involving design, software, and validation. Your ability to drive technical excellence and foster teamwork makes you an invaluable asset to any organization. If you’re ready to guide Synopsys’ next generation of mixed signal IPs and shape the future of technology, this opportunity is for you.

What You’ll Be Doing:

• Architecting and implementing SystemVerilog/UVM-based testbenches and verification flows for mixed signal IPs such as UCIe/DDR/Die-to-Die interfaces.
• Developing, executing, and driving closure for comprehensive verification plans and coverage metrics.
• Debugging RTL issues, managing regressions, and leading root cause analysis for failures.
• Guiding and mentoring junior engineers, establishing verification standards and best practices.
• Collaborating with design, software, and validation teams to ensure seamless project delivery and integration.
• Evaluating and championing new verification tools, automation scripts, and methodologies to drive innovation.

The Impact You Will Have:

• Elevate the quality and reliability of Synopsys’ mixed signal IPs, directly impacting the success of global semiconductor partners.
• Accelerate innovation in chip design and verification, contributing to industry-leading products and solutions.
• Mentor and empower the next generation of engineers, fostering a culture of excellence and growth.
• Drive adoption of best-in-class verification standards, enhancing productivity and efficiency across teams.
• Enable seamless integration of complex IPs by bridging design, software, and validation disciplines.
• Champion advanced verification technologies, positioning Synopsys as a leader in digital design automation.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering or related field.
• 10+ years proven experience in RTL design and verification of IP, ASIC, or SoC projects.
• Expert knowledge in HDLs (Verilog/VHDL/SystemVerilog) and digital logic fundamentals, including mixed AMS verification.
• Deep expertise in SystemVerilog/UVM, constrained random and directed verification, and coverage-driven flows.
• Proficiency in EDA tools (VCS, Questa, etc.), regression management, and automation scripting.
• Strong scripting skills (TCL, Perl, Python) for automation and process enhancement.
• Familiarity with standard protocol verification (AMBA, PCIe/UCIe, DDR, etc.) and CAD environments.
• Exposure to gate-level netlist creation and advanced verification techniques.
• Knowledge of AI/ML technologies is a plus.

Who You Are:

• Analytical thinker with a keen eye for detail and problem-solving.
• Effective communicator and team player, comfortable working in cross-functional and multi-geographical teams.
• Self-motivated leader who inspires and mentors others.
• Adaptable and open to learning new technologies and methodologies.
• Proactive innovator, always seeking ways to improve processes and outcomes.

The Team You’ll Be A Part Of:

You’ll join a passionate group of engineers in Bangalore, dedicated to developing and verifying cutting-edge mixed signal IPs. The team thrives on collaboration, continuous learning, and technical excellence, working closely with global counterparts in design, software, and validation. Together, you’ll deliver industry-defining solutions that power tomorrow’s technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.