Synopsys

Alternate Job Titles:

• ASIC Digital Design Sr Staff Engineer/ Principal Engineer
• Digital Verification Sr Staff Engineer/ Principal Engineer
• Sr Staff ASIC Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification. You thrive in a collaborative environment and have a keen eye for detail. Your technical expertise is complemented by your ability to communicate effectively and work well within a team. You are self-motivated and enthusiastic about technology and problem-solving. With a minimum of 5 years of experience in design verification, you have honed your skills in using simulation tools, scripting languages, and advanced verification techniques. You have a solid understanding of digital and mixed-signal designs and are eager to contribute to cutting-edge technologies that enable Data Center, AI/ML, and 5G applications.

Responsibilities & Technical Execution:

• Resolve significant and unique technical challenges, analyzing complex situations and data—including intangibles and trade-offs—to determine the most appropriate actions.
• Exercise independent judgment in selecting and applying advanced verification methods, techniques, tools, and evaluation criteria to achieve critical project and business outcomes.
• Lead technical direction and execution for mission-critical projects, serving as the top technical authority and providing final sign-off on major design and verification decisions.
• Develop, refine, and standardize verification methodologies, frameworks, and best practices, ensuring their adoption across teams and projects.
• Coordinate and align global, cross-functional teams (Design, DFT, Analog, Software, Validation, Customer) to drive informed decision-making and resolve conflicts.
• Mentor, motivate, and influence engineers at all levels, fostering a collaborative and high-performance culture both internally and with external partners.
• Proactively manage and resolve technical and organizational conflicts, and continuously improve verification and development processes to balance quality, schedule, and scalability.
• Demonstrate strong business awareness, understanding customer impact, product strategy, risk management, and cost/schedule trade-offs; make critical decisions that directly influence product quality, customer success, and business outcomes.
• Guide and participate in the development and validation of complex digital and mixed-signal verification solutions for high-speed interface IP.
• Define and review verification strategies, including test plans, checklists, coverage, assertion planning, and closure metrics.
• Architect and oversee the creation of robust verification environments from functional and micro-architecture specifications.
• Drive the application of advanced verification techniques such as constrained random generation, functional coverage, assertions, and formal verification.
• Review and ensure quality of test cases, checkers, scoreboards, and coverage models against verification objectives.
• Lead and troubleshoot complex simulation and debug efforts, including mixed-signal and real-number modeling using SystemVerilog.
• Oversee RTL, GLS, co-simulation, and coverage closure across projects.
• Lead and participate in technical and architectural reviews, providing guidance on risk, quality, and readiness.
• Act as a senior technical interface for customers, supporting IP bring-up, debugging, and methodology alignment in customer simulation environments.
• Champion continuous improvement of verification flows, automation, and development processes to ensure scalable, high-quality delivery

What You’ll Need:

• BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
• 10+ years of experience in design verification.
• Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal).
• Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus.
• Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

Who You Are:

• Highly responsible and result-oriented.
• Excellent English communication skills, both verbal and written.
• A great team player, willing to support others.
• Self-motivated and highly enthusiastic about technology and solving problems.

The Team You’ll Be A Part Of:

You will join a highly motivated and talented engineering team in Vietnam, working alongside experts from around the world. The team is dedicated to developing and validating complex digital and mixed-signal IP, driving innovation in Data Center, AI/ML, and 5G applications.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.