Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. 

ASIC Digital Design, Sr Engineer

We're looking for ASIC Digital Design Sr Engineer to join our team.
Does this sound like a good role for you?

The candidate will be a key member of the Synopsys DesignWare ARC Processor hardware team working on next-generation ARC processor Verification. Responsibility includes development and maintenance of HW-SW Co-Simulation, development of Testbenches and automation, resolving mismatches between design and C-model, development of C-models, functional coverage model creation and report analysis, code coverage analysis, integration of third party and internal verification IP, regression management. Candidate is expected to work with multi-site, multi-time zone, multi-cultural teams on various aspects ARC processor verification.

Key Qualifications

• Bachelor’s degree in engineering is required as a minimum 
• Requires a 2+ years of related experience
• Good Digital Design Knowledge is must
• Microprocessor architecture knowledge is a big plus
• Good written, verbal and analytical skills desired
• Experience in following areas is preferred:
  • HDL and Verification languages: SystemVerilog, Verilog
  • Programming skills  : C, C++, assembly, Python, Per,  makefile generation
  • Tools: RTL Simulators, eg VCS

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.