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General Information

Job Title
RTL engineer
Job ID
5545
Country
Viet Nam
City
Da Nang
Date Posted
03-Sep-2024
Job Category
Engineering
Job Subcategory
ASIC Digital Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
Job Descriptions
  • Responsible for specification development, RTL development for High Bandwidth Interface PHY IP.
  • Collaborate with Verification team and review the Verification plan mapping with specification.
  • Familiar with RTL to GDS flow to follow up with other teams during the logic implementation phases.
  • Locate: DaNang, Hanoi (need onboard in Danang for 4 first months)
Skills Requirements
  • BS/MS/PhD in Electronics Engineering, Telecommunications.
  • 2+ years of experience in RTL design for ASIC or PHY IP.
  • Familiar with tool VCS, Verdi, Spyglass or similar tools
  • Solid knowledge on clock domain crossing
  • Solid scripting skills (Perl, tcl, Python)
  • Familiar with APB, JTAG
  • Good communication both verbally and in writing
  • Experience in Analog Mixed Signal IP is a big plus
  • Good English in both speaking and writing.
  • Highly responsible, result oriented.
  • Self-motivated and highly enthusiasm in technology and solving problems

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.