Synopsys

Synopsys ARC Processor R&D -ASIC Digital Design 

We are a team working on producing the highly optimized hardware IP for the ARC family of configurable processors. We are looking for an engineer like you to be part of the team to work on our world-class micro-processors that allow our customers to develop highly optimized and sophisticated embedded designs 

https://www.synopsys.com/designware-ip/processor-solutions.html 

ASIC Digital R&D Engineer 

Key responsibilities: 

• To develop and maintain our micro-processor hardware IP including specification, implementation, verification & FPGA validation 

• To optimize designs for performance, area and power 

• To develop new tests for hardware IP verification/validation and improve functional/code coverage by using state-of-the-art verification/validation methodology 

• Interact with tools, modeling and simulation teams globally to deliver optimized solutions for our customers 

Job Requirements: 

• Strong desire to work with embedded processors or processor-based systems 

• Knowledge of HDL design and ideally, RISC architectures, DSP, AI, multi-core, etc. 

• Understanding of design/verification languages such as, SystemVerilog, Verilog 

• Knowledge of tools such as, RTL Simulators, e.g. VCS  

• Familiar with FPGA design flow and tools (Synplify, Vivado, Quartus), including constraint setup, synthesis, P&R and timing closure 

• Scripting/programming skill in assembler, C, Tcl, Perl/Csh desired 

• Good analysis and problem-solving skills 

• Excellent written and verbal skills including: Written and spoken English, Detailed status reporting; Ability to present results to the program management teams 

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.