Synopsys

Job Description: Seeking a highly motivated and innovative verification engineer with strong theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, the candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA, and USB products. The position offers an excellent opportunity to work with an expert team of digital, analog and mixed signal engineers responsible for delivering high-end mixed-signal designs.

Job Responsibilities:

• Modifying/using the existing UVM and VMM SystemVerilog testbenches to co-simulate mixed signal designs in both analog and digital coexist environment
• Analyzing/verifying the functionalities of high speed SERDES
• Defining and tracking verification testplans
• Debugging simulation failures in both analog and digital domains
• Creating top level analog testbenches for SERDES

Job Requirements:

• BTech/MTech plus at least 7 years of digital design and verification experience in the industry.
• Candidates should have experience writing scripts in languages such as Perl, Python and Unix shell.  The ideal candidate would be familiar with Verilog and SystemVerilog.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.