Synopsys

• 3 to 5 year experience in Digital verification using UVM/VMM methodology. 
• Good Knowledge on Verilog , system Verilog, VMM/UVM methodologies. Ability to create and debug mixed signal testbenches as per the design requirements.
• Implementing mixed signal checkers and measurements for the verification of mixed signal design
• Good knowledge on scripting languages like perl, python.
• Right attitude for exploring the design verification environment and come up with solutions for improving the flow/methodologies

Job description:

• Selected candidate will be a part of highly motivated and challenging high speed PHY design team working on latest technologies

Opportunity to work with different design and verification teams across globe.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.