Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. 


Digital IP DDR Controller Team is seeking for a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a particularly experienced digital IP design and verification team, targeting the current and next generation DDR memory controller. Theoretical and practical background in DDR memory is a solid plus. The position offers an excellent opportunity to work with a team of professional engineers who are responsible for delivering enhanced universal DDR memory controller from defining specification to performing functional and performance tests. 


Key Qualifications
BSEE with 8+ years or MSEE with 5+ years of relevant experience in the industry
Good experience in ASIC RTL design at both chip level and block level
Must be familiar with Verilog language
Good knowledge of digital design and synthesis constraints and flows
Good knowledge of VCS and DC/PT tool
Theoretical and practical background in DDR memory is a solid plus
Knowledge of high speed interface protocols, such as CHI, AXI, AHB, DFI, is a solid plus
Knowledge of System Verilog, UVM and Verification Methodology is a solid plus
Scripting experience in Shell, Perl, Python and TCL is a plus
Demonstrates good skills to analysis and solve problems
Demonstrates good skills to communicate with both local and global team members


Preferred Experience
RTL coding, and writing complex system-level test-benches in Verilog 
Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.