Skip to content

General Information

Job Title
ASIC Digital Design, Verification Staff Engineer
Job ID
6209
Country
India
City
Noida
Date Posted
11-Sep-2024
Job Category
Engineering
Job Subcategory
ASIC Digital Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
Job Description and Requirements :
Key responsibilities:
  • Identify verification environment requirements from its various sources (Specifications, Design functionality, Interfaces, etc …)
  • Generate verification test plan, verification environment documentation and test environment usage documentation
  • Support in defining, development, and verification of complex UVM verification environments
  • Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage)
  • Identify design problems, possible corrective actions and/or inconsistencies on documented functionality
Key Qualifications
  • Proven desire to learn and explore new state of the art technologies
  • Demonstrate good written and spoken English communication skills
  • Demonstrate good review and problem-solving skills
  • Knowledgeable with Verilog, VHDL and/or SystemVerilog
  • Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus
  • Understanding of verification methodology such as UVM /OVM
  • Good organization and communication skills
  • 5+ years of relevant experience

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.