Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary and seasoned engineering leader, driven by a passion for innovation in ASIC physical design. Seeking a highly motivated and innovative ASIC Physical Design Implementation Engineer to lead the Test Chip PHY development. You will lead a team of engineers to develop Test Chips for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with a focus on digital design.

What You’ll Be Doing:

Lead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles
Resource & Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution.

Floor planning & Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture.

Synthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.

Timing Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff.

Design Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips.

Block/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros.

Tool Flow Enhancements & Debug: Drive tool flow automation and debugging to improve productivity and design reliability.

Collaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development

Release & Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists

What You’ll Need:

• 12+ years of proven experience in ASIC physical Design, with expertise in leading complex SoC or test chip implementations at advanced process nodes.
• Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, LVS/DRC, and related methodologies.
• Demonstrated experience leading engineering teams and managing cross-functional projects in high-pressure environments.
• Familiarity with test chip methodology, IP integration, and advanced verification flows.
• Proficiencywithstate-of-the-artCAD tools such as DC, PT, ICC2/FC, ICV, Calibre, RedHawk, and advanced technologies like FinFet.
• Strong communication, problem-solving, and project management skills.

The Impact You Will Have:

• Elevate Synopsys’ leadership in advanced ASIC and IP development by delivering high-performance, reliable test chips.
• Enable rapid validation and integration of DDR/HBM/UCIe protocols, supporting next-generation silicon innovation.
• Enhance cross-functional collaboration, accelerating project timelines and improving overall design quality.
• Drive process improvements through tool flow automation, setting new standards for productivity and design reliability.
• Ensure robust manufacturability and performance, reducing risk and increasing success rates in foundry tape-outs.
• Mentor and develop junior engineers, fostering a culture of technical excellence and continuous learning.
• Contribute to the creation of industry-leading mixed-signal IPs, elevating Synopsys’ portfolio and market position.

Who You Are:

• Innovative thinker with a passion for solving complex engineering challenges.
• Inspirational leader who empowers teams and fosters collaborative, inclusive environments.
• Meticulous and detail-oriented, committed to quality and design integrity.
• Adaptable and resilient, thriving in fast-paced, dynamic settings.
• Excellent communicator, able to articulate technical concepts to diverse audiences.
• Continuous learner, eager to stay at the forefront of technology and industry trends.

The Team You’ll Be A Part Of:

You’ll join a highly skilled, multidisciplinary team focused on developing industry-leading test chips for cutting-edge protocols like DDR, HBM, and UCIe. The team values collaboration, innovation, and technical excellence, working closely with architecture, RTL, circuit, and verification experts to deliver best-in-class mixed-signal IP solutions. Together, you’ll shape the next generation of silicon technology and drive Synopsys’ continued success in the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.