Synopsys

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent 15+ years in the trenches of ASIC physical design, and you know that the difference between a chip that tapes out on time and one that misses the window is usually a decision made during floorplanning or a timing path someone should have flagged three weeks earlier. You are the kind of leader who can spot that path, explain why it matters, and rally the team to fix it without creating panic or rework downstream.

Managing people energizes you. You care about growing engineers who can own a block from floorplan to signoff, and you know that means pairing the right mentor with the right challenge at the right time. You are comfortable sitting in a customer review explaining a PPA tradeoff and then walking back to your team to translate that feedback into actionable next steps. At Synopsys, you will lead a team building test chips that push the boundaries of what is possible at the most advanced nodes in the industry.

What You'll Be Doing

• Lead end-to-end physical implementation of multi-project test chips across 2nm, 3nm, 4nm, 5nm, and 7nm nodes, from floorplanning through GDSII signoff
• Manage and mentor a team of physical design engineers, balancing hands-on technical guidance with strategic leadership and career development
• Drive project planning, resource allocation, and budget management to meet delivery timelines and quality targets across concurrent programs
• Collaborate daily with RTL, verification, and product engineering teams to align on requirements, resolve integration issues, and ensure seamless handoffs
• Interface directly with customers and stakeholders to gather design requirements, provide status updates, and manage expectations throughout the project lifecycle
• Optimize physical design flows using Synopsys EDA tools (ICC2, Fusion Compiler, PrimeTime, StarRC) to achieve best-in-class PPA and meet signoff criteria
• Establish and enforce design closure methodologies, STA practices, and quality standards that scale across multiple projects and technology nodes

The Impact You Will Have

• Deliver complex, high-performance ASIC designs on schedule that enable Synopsys customers to compete and win in the semiconductor market
• Set the technical standard for physical implementation across the Bangalore design team, influencing methodologies that will be adopted across future programs
• Build a bench of skilled physical design engineers who can independently own blocks, mentor peers, and drive technical decisions with confidence
• Strengthen customer relationships by consistently meeting commitments, responding to feedback with speed, and delivering designs that exceed PPA expectations
• Drive measurable improvements in design efficiency, turnaround time, and tool utilization through process optimization and flow automation
• Contribute to Synopsys' reputation as the EDA partner of choice by delivering test chips that demonstrate what is achievable at the cutting edge of process technology
• Shape the roadmap for physical design capabilities at advanced nodes, feeding lessons learned back into tool development and customer engagement

What You'll Need

• 15-20+ years of hands-on experience in ASIC physical design, with proven delivery of complex designs at 7nm or more advanced nodes (5nm, 3nm, 2nm)
• Deep technical expertise across the full physical implementation flow including floorplanning, placement, CTS, routing, timing closure, and signoff
• Strong understanding of front-end design processes (RTL, synthesis, verification) and how they impact backend implementation and PPA
• Demonstrated leadership managing and developing engineering teams of 10+ people, with a track record of building high-performing, collaborative groups
• Proficiency with Synopsys physical design and signoff tools (ICC2, Fusion Compiler, PrimeTime, StarRC, RedHawk) and the ability to optimize flows for advanced nodes
• Experience managing project schedules, budgets, and cross-functional dependencies in a customer-facing or product development environment
• Excellent communication skills, you can explain a complex timing closure strategy to a customer executive and then translate it into a sprint plan for your team

Who You Are

• You can walk into a war room during a timing crisis, assess the critical paths, and decide in real time whether to adjust the floorplan, repartition the design, or push back on a constraint, and you can explain that call to both your team and your customer
• You treat mentorship as part of the job, not an extra, you pair junior engineers with the right challenges, review their work with specificity, and celebrate their wins publicly
• When a project slips or a signoff metric misses target, you do not look for someone to blame, you gather the team, diagnose the root cause, and build a recovery plan that people actually believe in
• You are organized enough to manage five concurrent projects without losing track of who owns what, and you are disciplined about keeping stakeholders informed before they have to ask
• You push back when a customer requirement does not make technical sense or a schedule is not realistic, and you do it in a way that builds trust rather than friction
• You stay current on advanced node challenges, FinFET vs. GAA tradeoffs, multi-patterning constraints, electromigration at low voltage, because you know those details matter when you are trying to close timing at 2nm

The Team You'll Be Part Of

You will be joining a high-impact team of physical design engineers at Synopsys' Bangalore site. The team is dedicated to delivering state-of-the-art ASIC solutions for leading global customers, working closely with cross-functional groups and leveraging the latest EDA technologies. As a leader, you will play a key role in shaping the team's technical direction, fostering collaboration, and driving excellence in every project.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.