Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate, detail-oriented engineer who thrives in collaborative and fast-paced environments. Your expertise in ASIC physical design makes you a go-to resource for solving complex challenges in silicon implementation. You enjoy mentoring others and sharing your knowledge, contributing to the technical growth of your team. You are driven by innovation and are always eager to stay at the forefront of technology, adapting quickly to new tools, methodologies, and process nodes. You possess a deep understanding of the full physical design flow and are comfortable navigating the intricacies of SoC floorplan, timing closure, and signoff processes. Your strong analytical skills enable you to optimize designs for power, performance, and area, while your scripting abilities allow you to automate and streamline workflows. You communicate clearly and effectively in English, fostering strong connections across cross-functional teams. Above all, you value teamwork, believe in continuous improvement, and are committed to delivering high-quality silicon solutions on schedule. Whether mentoring junior engineers or leading technical initiatives, your leadership and collaborative spirit drive the success of projects and the advancement of Synopsys’ mission.

What You’ll Be Doing:

• Leading block-level and chip-level physical design activities from netlist through final implementation (RTL to GDSII).
• Driving floorplan:block shaping, power planning, pin and macro placement, special routing and ESD considerations to meet customer requirements
• Placement, clock tree synthesis, poststained routing optimizations for timing, power, area, congestion and signal integrity to meet stringent project requirements.
• Signoff timing, EMIR and physical verification analysis and closure with ECOs
• Partnering with Cross functional (, Implementation, DFT, packaging, foundation IPs, MBIST) teams to achieve hardening closure goals.
• Developing and improving automation scripts and methodologies to increase physical design efficiency and quality.
• Investigating and resolving design, tools, flow, and machine issues throughout the implementation cycle.
• Mentoring junior engineers and providing technical leadership across the team.

The Impact You Will Have:

• Ensuring successful hardening of complex subsystems projects and test chip tape outson schedule.
• Driving improvements in design efficiency, methodology, and automation within the team.
• Enhancing cross-functional collaboration to solve multidisciplinary challenges in  SoC design.
• Contributing technical leadership and mentoring to foster a culture of growth and excellence.
• Delivering high-quality silicon solutions that power advanced technologies and accelerate innovation
• Increasing the competitive edge of Synopsys by enabling the creation of best PPA and reliable SoCs.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, ora related field.
• Strong experience in ASIC physical design and implementation.
• Hands-on knowledge of full physical design flow, including floor plan, optimizations, and signoff closure.
• Experience with advanced process nodes and IP integration challenges in complex SoCs.
• Strong understanding of STA, EMIR and physical verification concepts.
• Proficiency with industry-standard implementation and signoff tools such as Synopsys Fusion Compiler, PrimeTime, Redhawk, ICV and similar.
• Scripting experience in Python/Tcl/Perl,bash, make file and version control
• Excellent written and verbal communication skills in English.
• Demonstrated ability to work effectively in cross-functional teams and build strong network relationships.

Who You Are:

• Analytical and detail-oriented, with a strong problem-solving mindset.
• Collaborative and communicative, able to work effectively with diverse teams.
• Proactive and innovative, continuously seeking ways to improve processes and methodologies.
• Mentorship-oriented, eager to support and guide junior engineers.
• Adaptable and resilient, thriving in dynamic and challenging environments.

The Team You’ll Be a Part Of:

You’ll join a dynamic and highly skilled engineering team focused on delivering world-class SoC solutions. The team values collaboration, technical excellence, and continuous learning, working together to solve complex challenges and drive innovation in silicon design. You’ll have opportunities to engage with experts across RTL, Implementation, DFT and MBIST, packaging, foundation IPs, contributing to a culture of shared knowledge and mutual support.