Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and driven engineer with a deep curiosity for emerging technologies and the courage to tackle complex challenges head-on. With over 6 years of experience in ASIC physical design, you have honed your expertise across multiple domains and thrive in environments that demand both independent judgment and collaborative problem-solving. You excel at analyzing intricate technical problems, devising innovative solutions, and adapting quickly to new tools and methodologies. Your communication skills enable you to bridge teams across geographies, and you bring a positive, inclusive attitude to every interaction. Whether leading projects, mentoring junior colleagues, or representing your team in business-wide initiatives, you demonstrate reliability, attention to detail, and a commitment to excellence. You seek opportunities to grow, contribute, and make a tangible impact on world-class IP implementation at cutting-edge technology nodes. If you are excited by the prospect of working on challenging timing closure, macro IP integration, and efficient clock tree design, while collaborating with diverse teams, you will thrive in this role.

What You’ll Be Doing:

• Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality.
• Driving timing closure efforts, especially above ~2GHz, and resolving complex challenges related to mixed signal and macro IP integration.
• Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements.
• Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams.
• Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects.
• Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation.

The Impact You Will Have:

• Accelerate the delivery of high-performance DDR/HBM/HBI IP solutions to Synopsys customers worldwide.
• Enhance product reliability, scalability, and innovation by addressing technical challenges in timing closure and macro integration.
• Drive adoption of advanced physical design methodologies, influencing industry standards and best practices.
• Strengthen cross-functional collaboration, building bridges between global teams and fostering knowledge sharing.
• Shape the future of semiconductor technology by contributing to projects at the forefront of silicon innovation.
• Support Synopsys’ reputation as a leader in IP implementation, ensuring customer satisfaction and successful deployments.

What You’ll Need:

• Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications.
• Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC).
• Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration.
• Strong analytical and problem-solving skills, with a track record of resolving complex technical issues.
• Ability to independently lead project tasks, mentor junior team members, and work collaboratively.

Who You Are:

• Excellent communicator, capable of articulating technical concepts to diverse audiences.
• Strong team player, fostering inclusivity and collaboration across global teams.
• Adaptable and eager to learn new technologies and methodologies.
• Creative thinker, bringing innovative approaches to solving design challenges.
• Detail-oriented, reliable, and committed to delivering high-quality results.

The Team You’ll Be A Part Of:

You will join the SNPS DDR/HBM/HBI IP implementation team—a dynamic group responsible for delivering world-class IP at the most advanced technology nodes. The team thrives on technical excellence, collaboration, and continuous learning, working closely with counterparts in Bangalore and the US to solve some of the industry’s toughest challenges. Together, you will push the boundaries of what’s possible in silicon design.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.