Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and highly-skilled engineer eager to make a tangible impact in the world of semiconductor innovation. Your strong technical foundation in ASIC physical design is complemented by a collaborative mindset and an eagerness to solve complex challenges. You thrive in a dynamic, multicultural environment, seamlessly engaging with both local and international colleagues. Your attention to detail and perseverance shine through when tackling tight timing closures and integrating mixed-signal macro IPs. You possess a deep understanding of advanced technology nodes, including 10nm, 7nm, 6nm, and below, and are excited to work on world-class DDR IP implementation. You are a proactive communicator, adept at translating technical concepts into actionable solutions, and you excel in balancing rigorous technical requirements with practical design constraints. As a continuous learner, you stay updated on emerging industry trends and best practices, and your integrity and reliability make you a trusted member of the team. If you’re ready to push the boundaries of silicon design and collaborate with some of the brightest minds in the industry, Synopsys is your ideal next step.

What You’ll Be Doing:

Implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).

Performing timing closure for designs operating above ~4GHz, ensuring robust performance and reliability.

Collaborating daily with local and US counterparts to align on technical challenges and project milestones.

Integrating mixed-signal macro IPs and optimizing their placement within complex chip architectures.

Designing and building efficient clock trees with exceptionally tight skew balancing to meet stringent requirements.

Driving continuous improvement in implementation methodologies and sharing best practices across the team.

Participating in design reviews, providing critical feedback and innovative solutions to enhance project outcomes.

The Impact You Will Have:

Enabling high-performance DDR IP integration, which powers next-generation computing, networking, and storage solutions.

Accelerating the delivery of silicon chips at cutting-edge technology nodes, advancing Synopsys’ leadership in the industry.

Strengthening Synopsys’ reputation for innovation and reliability through your technical expertise and dedication.

Contributing to successful project execution by bridging technical knowledge between global teams.

Driving quality improvements and efficiency in physical design processes, setting new standards for excellence.

Mentoring and guiding junior engineers, helping build a stronger, more resilient team.

What You’ll Need:

Strong technical concepts with 4+yrs in ASIC physical design.

STA for High Performance Designs like DDR/LPDDR,HBM and SOC.

Responsible for timing closure activities for High performance IPs

Close the design to meet timing , power and area requirements.

Implement engineering change orders (ECO) to rectify functional bugs and timing issues.

Ensure qualiity and efficiency of RTL2GDS implementation process.

good Automation background in Python, Perl , TCL, Shell scripting.

Good to have hands on experience in Physical Design, STA and similar domains.

Skill Set

Good knowledge and hands-on experience in static timing analysis (closing timing at chip level)

Good understanding of timing constraints.

Should have experience inhandling asynchronous timing , multiple corner timing closure

Familiar with PT , PTECO and DMSA

Proficient in scripting languages (Tcl and Python).

Ability to communicate effectively with multiple global cross-functional teams. Effective presentation skills.

The Team You’ll Be A Part Of:

You'll join the SNPS DDR IP implementation team—a diverse, innovative group focused on delivering world-class DDR IP solutions at the forefront of technology. The team values collaboration, knowledge-sharing, and a commitment to excellence, working closely with both local and US counterparts to achieve remarkable results in silicon design and integration.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.