Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary leader with a deep understanding of analog and mixed-signal design. With at least 8 years of experience in CMOS circuit design and layout methodology, you have a proven track record of leading complex projects from conception to completion. Your expertise extends to deep submicron process technologies, and you are familiar with analog mixed-signal simulation strategies. Your ability to navigate and resolve issues, coupled with your strong leadership qualities, enables you to guide teams effectively to meet schedules and achieve project goals. You excel in cross-functional settings, demonstrating excellent communication skills and the ability to mentor and advise team members. Your familiarity with JEDEC standards for DDR interfaces and a solid understanding of signal and power integrity further enhance your capability to deliver innovative solutions in high-performance IP development.

What You’ll Be Doing:

• Leading the development of next-generation DDR/HBM/UCIe IPs.
• Advising team members to meet schedules and resolve problems effectively.
• Taking on project leadership roles and contributing to complex project aspects.
• Developing and maintaining project schedules, ensuring timely delivery.
• Collaborating in cross-functional settings to drive project success.
• Demonstrating proficiency in design and verification processes.

The Impact You Will Have:

• Driving innovation in next-generation DDR/HBM/UCIe IP development.
• Enhancing the performance and capabilities of our Silicon IP portfolio.
• Ensuring high-quality and efficient project execution.
• Mentoring and guiding team members to achieve their full potential.
• Contributing to the rapid integration of advanced technologies into SoCs.
• Helping Synopsys maintain its leadership in the semiconductor industry.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 8+ years of experience in CMOS circuit design and layout methodology.
• In-depth understanding of analog/mixed-signal circuitry and ESD concepts.
• Familiarity with analog mixed-signal simulation strategies.
• Knowledge of JEDEC standards for DDR interfaces and ASIC design flow.

Who You Are:

• Visionary leader with strong problem-solving skills.
• Excellent communicator with the ability to lead and mentor teams.
• Detail-oriented and proficient in project management.
• Adaptable and able to thrive in cross-functional settings.
• Committed to achieving high standards of product quality and efficiency.

The Team You’ll Be A Part Of:

Join a dynamic and innovative team focused on developing cutting-edge DDR/HBM/UCIe IPs. Our team is dedicated to pushing the boundaries of what's possible in silicon IP design, working collaboratively to deliver high-performance solutions that drive the next wave of technological advancements. Together, we are committed to excellence, innovation, and continuous improvement.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.