Descriptions & Requirements
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
We are hiring highly competent technical experts for our next generation memory interface PHY IPs (DDR/HBM/UCIe).
Responsibilities:
- To be part of next generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) development
- Execute projects in advanced technologies while demonstrating good analytical and problem-solving skills
- Develop high-speed IO designs for memory interface PHY IP in CMOS/FinFET/GAA
Requirements-
- Qualification: BTech/MTech
- Proficient in analog design fundamentals, device physics
- Knowledge of deep submicron process technologies.
- Understanding of reliability concepts
- Ability to execute assigned circuit design tasks with best product quality and efficiency
- Good communication and interpersonal skills
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, or disability.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.