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General Information

Job Title
Analog Design, Sr Manager
Job ID
4798
Country
India
City
Hyderabad
Date Posted
03-Sep-2024
Job Category
Engineering
Job Subcategory
Analog Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
Overview
 
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
 
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
 
The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP Prototyping Kits and IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. At Synopsys, you will have the opportunity to find the perfect blend of our proven EDA presence and our broad IP portfolio.
 
Our Solution Group's Central IP team in Hyderabad India is looking for an exceptional and enthusiastic Sr Manager to join our team. This candidate will be part of Synopsys Mixed-Signal Interface IP BU's responsible for specifying, architecting, executing and productizing critical analog building blocks in high-speed interface SerDes, DDR, HBM, UCIe and beyond IPs.
 
Responsibilities
 
  • Lead and manage a team of analog design engineers at various level of experiences
  • Main tasks include overall project planning and execution, schedule risk and priority management, providing technical direction and guidance, fostering innovation, performance reviews, team talent development
  • Work closely with cross functional teams across different geographies , wide variety of backgrounds and time zones to ensure engagement and execution
  • Take the lead role in architectural definition of design implementation of various state-of-the-art, high speed and low power analog/mixed-signal designs for high-speed interfaces
  • Other responsibilities include layout supervision, design documentation, design reviews, customer interaction and post silicon activities support
 
 
Qualifications
 
  • BSEE degree and 18-25 years of analog/mixed-signal IC design, or MSEE/PhD with 15-20 years of experience
  • Experience managing, mentoring, guiding and growing engineering teams
  • Direct design experience in high speed PHY such as SERDES, DDR or HBM is a strong plus
  • Proficiency with spice simulators including HSPICE, PrimeSim/FineSim and XA
  • Deep knowledge on DC/AC/Transient, Cross corners PVT, Static & Dynamic CCK, Equivalency checks, Aging, EMIR/SHE Reliability analysis, Monte Carlo simulations
  • Must be a team player with good written and verbal communication skills, self-motivated, thorough design styles, detail oriented, and work with multiple functional teams with good engineering practices
  • Understanding of behavioral Verilog models & experience in SystemVerilog for AMS circuits
  • Prior experience on products/test chips bring up, lab debug and simulations to silicon correlation is highly desirable
  • Ability to provide automation​ for rapid and dynamic design needs is highly sought-after

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.