Synopsys

Alternate Job Titles:

• Senior AMS Timing Supervisor
• Analog Mixed Signal Design Lead
• Timing Model Design Manager

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned engineer with a strong background in analog and mixed signal circuit design. You excel at solving timing challenges, collaborating with diverse teams, and mentoring junior engineers. Your expertise with industry tools and your commitment to quality make you a valuable leader. You communicate effectively and thrive in dynamic, innovative environments.

What You’ll Be Doing:

• Develop accurate timing models for macros used in multi-die designs. 
• Perform analysis and verification to ensure timing models meet all performance, reliability, and design requirements. 
• Collaborate closely with IP design teams to maintain high-quality timing arcs and adhere to timing methodology standards. 
• Assist in timing analysis and closure for high-speed interfaces and mixed-signal IP blocks. 
• Perform STA (Static Timing Analysis) using industry-standard EDA tools. 
• Support constraint development and validation for timing sign-off. 
• Collaborate with design, verification, and physical implementation teams to resolve timing issues. 
• Utilize SiliconSmart for SPICE-based characterization and NanoTime for transistor-level Static Timing Analysis (STA). 

The Impact You Will Have:

• Enhance performance and reliability of interface designs.
• Improve design quality across projects.

• Advance timing methodologies and best practices.
• Mentor and grow engineering talent.
• Foster collaboration and innovation.
• Strengthen Synopsys’ reputation in AMS design.

What You’ll Need:

• BS/MS in Electronics, Electromechanics, or Telecommunications.
• 5-8 years in analog/mixed signal or custom logic design.
• Basic understanding of timing analysis, SPICE simulation, and STA concepts. 
• Scripting languages: Python, TCL for automation and data processing.
• Expertise in CMOS analog design and simulation tools.
• Proficiency with Cadence Virtuoso, SNSP tools, Hspice, Spectre.
• Strong English communication skills.

Who You Are:

• Team player, supportive and responsible.
• Results-driven and enthusiastic about technology.
• Motivated mentor and problem solver.

The Team You’ll Be A Part Of:

Join a collaborative engineering group focused on high-performance interface solutions and continuous innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details during the hiring process.