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General Information

Job Title
Analog Design, Sr Supervisor
Job ID
5032
Country
India
City
Bangalore
Date Posted
03-Sep-2024
Job Category
Engineering
Job Subcategory
Analog Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
 
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
We are hiring visionary leaders for our next generation DDR/HBM/UCIe PHY IP’s!
Responsibilities:
  • Sr Supervisor to help lead next generation DDR/HBM/UCIe IP development
  • Has leadership qualities and lead developments of new technologies while demonstrating good analysis and problem-solving skills
  • Acts as an advisor to employees to meet schedules and/or resolve problems
  • Perform in project leadership role and contributes to complex aspects of a project
  • Develop and maintain schedules, work in cross-functional settings while being proficient in design & verification
 
Requirements-
  • Qualification: BTech/MTech
  • Skills/Experience: 8+ years
  • Knowledge of CMOS processes and issues in deep submicron process technologies.
  • CMOS circuit design and layout methodology & flow; in-depth understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage.
  • Familiar with analog mixed-signal simulation strategies and having a good knowledge of Signal Integrity and/or Power Integrity is a plus.
  • Familiarity with ASIC design flow.
  • Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus.
  • Ability to lead projects with best product quality and efficiency.
  • Good written and verbal communication skills in interactions to lead development teams
 
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, or disability.
 

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.