Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are:

You will join a dynamic and collaborative team focused on mixed-signal design where you'll develop ASIC Physical Design Implementation of sub-blocks. The team is dedicated to SERDES design and the candidate will be dedicated to mastering all backend phases, including Synthesis, Place and Route, Timing Analysis and Physical Verifications. You will receive initial training from top field experts and engage in continuous on-the-job learning to stay ahead of technological advancements and daily challenges.

What You’ll Be Doing:

* Work in all backend stages: Synthesis, Place and Route, Timing  and Power Analysis and Physical Verifications;

* Provide ideas and create solutions to help on our daily work;

* Identify issues and provide possible corrective actions;

* Cooperate with other team members as well with other teams

What You’ll Need:

* Master degree in electronics engineering, computer science or similar;

* Experience in SOC Physical Implementation flows (preferred);

* Good knowledge on scripting and programing languages, such as tcl, shell, C and python;

* Fluent written and spoken English;

* Good communication and organizational skills;

* Willingness to learn new things;

* Problem-solving skills;

* Capability to work as a team member and promote excellent working relationships.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.