Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned professional with a strong background in SerDes and high-speed analog design. With a PhD and 5+ years of experience or an MSc and 8+ years of experience, you bring in-depth familiarity with transistor-level circuit design and a solid foundation in CMOS design fundamentals. You have a proven track record of implementing circuits for the TX, RX, and Clock paths within a SerDes, and detailed design experience with sub-circuits such as receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillators, phase interpolators, delay-locked loops, phase-locked loops, bandgap references, ADCs, and DACs. You are adept at optimizing FinFET CMOS layout to minimize the effects of parasitic resistance and capacitance and reduce local device mismatch and proximity effects. Your awareness of ESD issues and design for reliability, along with your experience with EDA tools for schematic entry, physical layout, and design verification, makes you an ideal candidate for this role. You are knowledgeable in SPICE simulators, Verilog-A for analog behavioral modeling, and simulation-control/data-capture, and proficient in scripting languages such as TCL, Perl, C, Python, and MATLAB.

What You’ll Be Doing:

• Reviewing SerDes standards and architecture documents to develop analog sub-block specifications.
• Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
• Proposing design and verification strategies that efficiently use simulator features to ensure the highest quality design.
• Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation.
• Collaborating with digital RTL engineers on the development of calibration, adaptation, and control algorithms for analog circuits.
• Presenting simulation data for peer and customer review.
• Mentoring and reviewing the progress of junior engineers.
• Documenting design features and test plans.
• Consulting on the electrical characterization of your circuit within the SerDes IP product.

The Impact You Will Have:

• Driving the development of cutting-edge SerDes technology that powers high-speed data transmission.
• Ensuring optimal performance, power, and area efficiency in our analog designs.
• Improving the quality and reliability of our designs through innovative verification strategies.
• Enhancing collaboration between analog and digital design teams to create cohesive solutions.
• Mentoring junior engineers, fostering their growth and development within the company.
• Contributing to the documentation and knowledge base that supports future design efforts.

What You’ll Need:

• PhD with 5+ years, or MSc with 8+ years of SerDes/High-Speed analog design experience.
• In-depth familiarity with transistor-level circuit design and CMOS design fundamentals.
• Silicon-proven experience implementing circuits for the TX, RX, and Clock paths within a SerDes.
• Detailed design experience with several SerDes sub-circuits such as receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillators, phase interpolators, delay-locked loops, phase-locked loops, bandgap references, ADCs, and DACs.
• Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and reduce local device mismatch and proximity effects.
• Awareness of ESD issues and design for reliability (e.g., electro-migration, IR, aging).
• Experience with EDA tools for schematic entry, physical layout, and design verification.
• Knowledge of SPICE simulators and simulation methods.
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB.

Who You Are:

You are a detail-oriented, analytical thinker with strong problem-solving skills. Your ability to work independently as well as collaboratively within a team makes you a valuable asset. You possess excellent communication skills, enabling you to convey complex technical information effectively to peers and customers. You are dedicated to continuous learning and staying updated with the latest advancements in analog design and technology. Your mentorship capabilities allow you to guide and nurture junior engineers, fostering a culture of knowledge sharing and innovation.

The Team You’ll Be A Part Of:

You will join a dynamic team of highly skilled engineers focused on pushing the boundaries of analog design. Our team thrives on collaboration, innovation, and a commitment to excellence. We work closely with digital RTL engineers, layout designers, and verification experts to deliver high-performance SerDes IP products that meet the evolving needs of our customers.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.