Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a motivated and detail-oriented Analog Layout Design Engineer with a passion for cutting-edge technology. You have a solid background in developing high-quality layouts, meeting stringent timelines and verification requirements. Your expertise lies in understanding deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies at 7nm and below. You possess strong problem-solving skills and have a track record of collaborating effectively with cross-functional teams. Your excellent communication skills allow you to convey complex technical concepts clearly and concisely. You are dedicated to fostering an inclusive work environment and are committed to continuous learning and improvement.

What You’ll Be Doing:

- Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. - Creating floorplans, routing, and performing physical verifications to meet quality standards. - Debugging and solving complex layout issues to ensure high-quality deliverables. - Collaborating with design engineers to optimize layout for performance, power, and area. - Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. - Ensuring compliance with DRC, LVS, ERC, and antenna rules.

The Impact You Will Have:

- Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. - Enhance the performance and reliability of next-generation semiconductor IPs. - Accelerate the time-to-market for high-performance silicon chips. - Reduce risks associated with layout design by adhering to stringent verification requirements. - Foster a collaborative and innovative work environment. - Support Synopsys' mission to lead in chip design and software security.

What You’ll Need:

- BTech/MTech in Electrical Engineering or related field. - 2+ years of relevant experience in analog layout design. - Proficiency in developing quality layouts and performing physical verifications. - In-depth understanding of deep submicron effects and floorplan techniques. - Experience with CMOS, FinFET, and GAA process technologies at 7nm and below. - Knowledge of layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

Who You Are:

- Detail-oriented with strong analytical skills. - Effective communicator with excellent written and verbal skills. - Collaborative team player who fosters accountability and ownership. - Innovative thinker with a problem-solving mindset. - Committed to continuous learning and professional development.

The Team You’ll Be A Part Of:

You will be joining a dynamic and innovative team focused on developing the next generation of DDR/HBM/UCIe PHY IPs. Our team values collaboration, inclusivity, and continuous improvement. We work together to push the boundaries of technology and deliver high-quality solutions that meet the needs of our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.