Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and skilled Analog Layout Design Engineer with a keen eye for detail and a deep understanding of advanced semiconductor technologies. You thrive in dynamic environments and possess a strong problem-solving aptitude. With a profound expertise in developing high-quality layouts and physical verification techniques, you are ready to contribute to cutting-edge DDR/HBM/UCIe IP development. You excel in collaboration, fostering accountability and ownership within teams, and have excellent written, verbal communication, and interpersonal skills. Your commitment to diversity and inclusion aligns with Synopsys’ values, and you are eager to work in an environment that welcomes all perspectives.

What You’ll Be Doing:

• Hands-on development of layout for next-generation DDR/HBM/UCIe IPs.
• Solving complex problems and debugging issues effectively.
• Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements.
• Ensuring compliance with DRC, LVS, ERC, and antenna rules.
• Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below).
• Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

The Impact You Will Have:

• Enhancing the performance and reliability of Synopsys’ DDR/HBM/UCIe IPs.
• Accelerating the integration of advanced capabilities into SoCs.
• Reducing risk and improving time-to-market for differentiated products.
• Driving innovation in semiconductor technology and design.
• Contributing to the success of Synopsys’ Silicon IP business.
• Fostering a collaborative and inclusive work environment.

What You’ll Need:

• BTech/MTech degree in a relevant field.
• 4+ years of experience in analog layout design.
• Proven track record in developing high-quality layouts and meeting verification timelines.
• Strong understanding of deep submicron effects and floorplan techniques.
• Exposure to layout matching, ESD, latch-up, EMIR, DFM, and LEF generation.

Who You Are:

• Detail-oriented with excellent problem-solving skills.
• Collaborative and able to foster accountability and ownership.
• Strong written, verbal communication, and interpersonal skills.
• Committed to diversity and inclusion.

The Team You’ll Be A Part Of:

You will be part of a dynamic team focused on developing next-generation DDR/HBM/UCIe PHY IPs. Our team values innovation, collaboration, and continuous improvement, driving the success of Synopsys’ Silicon IP business.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

job Description and Requirements

 At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

 Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

 We are hiring self-motivated individual contributors for our next generation DDR/HBM/UCIe PHY IP’s!

Responsibilities:
 * Hands on in layout development of cutting edged technologies for next generation DDR/HBM/UCIe IP development
* Good problem-solving and debugging skills
 * Work on layout floorplan, routing and physical verifications to meet quality requirements

 Requirements
* Qualification: BTech/MTech
* Skills/Experience: 4+ years relevant
 * Experienced in developing quality layout meeting timelines and verifications DRC, LVS, ERC, Antenna
 * Good understanding of deep submicron effects, floorplan techniques in CMOS, FinFET, GAA process technologies 7nm and below
 * Exposure to layout matching techniques, ESD, latch-up, EMIR, DFM, LEF generation
 * Collaboration with teams, foster accountability and ownership
 * Good written, verbal communication and interpersonal skills

 Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, or disability.