Synopsys

An exciting opportunity to work with Synopsys as a part of Synopsys Solutions Group.  

You will be responsible for ensuring Synopsys IP products meet quality targets. You will work closely with customers; you will work closely with various IP applications and R&D engineering teams to ensure smooth out-of-the-box experience for Synopsys Interface IP customers. 

• Collaborate with digital design, verification and application engineers to create and deliver tools and scripts that will enable them to solve a range of complex problems faster. 

• Verify the interoperability of various Synopsys IP solutions by executing various test strategies on controller and PHY integration. 

• Work on diverse range of interface IP products such as PCIe, DDR, AMBA, UFS and Unipro. 

Minimum Requirements 

• Knowledge of one digital design language such as Verilog, VHDL or SystemVerilog.  

• Understanding of digital design front end flow. 

• Excellent command over spoken and written English. 

• BS/MS degree in Engineering, Physics, applied mathematics, or any related field (high year students may also be considered for junior engineering positions). 

Preferred Requirements   

• Knowledge of digital design front end flow, exposure to back-end flow. 

• Experience and understanding of RTL simulations and synthesis as part of an ASIC or FPGA design flow. 

• Experience with one or more Interface Protocols such as DDR, Ethernet, USB, PCIe, AMBA etc. 

• Excellent digital design, simulation and debugging skills. 

• Experience with one scripting language such as python, perl, TCL or any other.  

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.