Synopsys

We're looking for Sr. Application Engineer to join our team.
Does this sound like a good role for you?

In this role, you will resolve a wide range of issues in creative ways on a regular basis. Customarily exercise independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is self-directed and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.

Key Qualifications

• Typically requires at least 10+ years of related experience
• Excellent communication, verbal and written, and awareness of project management issues
• Full understanding of specialization area plus working knowledge of many related areas

Job Description :

• Responsible for the development and implementation of technical solutions to customer problems as part of a project team
• Responsible for Synthesis and Timing Closure at Block/Sub-system or SoC level
• Responsible for performing the input/output deliverable sanity check (Constraints analysis, LDRC, LEC, Low-Power) at the RTL/Netlist-level to enable smooth timing closure
• Work closely with RTL design, DFT and Physical Implementation teams to meet timing closure goals
• Play a key role in understanding the design goals to meet performance/timing requirements, understand the clocking architecture and their relationship and lead timing related discussions at the Block/Sub-system or SoC level
• Responsible SoC/ASIC Top P&R Timing Closure including  ECO execution to meet Sign-off requirements
• Responsible SoC/ASIC  Top STA Timing Closure including  ECO execution  to meet Sign-off requirements

•   Experience in performing multi-mode/multi-corner timing closure of complex blocks/sub-systems of   SoC from synthesis to timing sign-off.
•   Experience with timing constraints (SDC) development and validation at block/sub-system level for     various modes. 
•  Ability to debug, analyze and provide solution to timing closure challenges at block/sub-system level.
• Ability to automate or write scripts using TCL, Perl or Python.
• Understanding of Low-power concepts  (UPF) and experience in performing low-power checks at the RTL/Netlist level.
• Experience in performing Logical Equivalence Checks (formal verification).
• Experience with Synopsys SDC, Fusion Compiler, ICC2, ICV, PrimeTime tools
• Bachelors or Masters degree with 10 years of experience in IC-Design/Semiconductor Engineering or related field.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.