Synopsys

Synopsys is uniquely positioned to offer the most complete verification solution in market today. 

ZeBu is the emulation platform of Synopsys verification flow, it’s the industry’s performance & capacity in Emulation. 

As a Senior AE for emulation, candidate will be responsible for successful deployment of Synopsys emulation solution to a growing customer base in China. 

The AE responsibilities include onsite deployment of industry emulation technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement. 

Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve complex design verification and software validation issues for customers cutting edge ASIC/SoC designs. The position offers a great opportunity to grow by learning state-of-art verification flows from Synopsys. 

Requirements: MS or PhD majored in EE with more than 5 years of IC design/verification/emulation/FPGA prototyping experiences. 

Real project experience in ASIC/SoC emulation or FPGA based design and verification, and good expertise on popular emulators like Palladium/Veloce/Zebu or FPGA compile/runtime/debug are required. 

Good knowledge of high-level design methodologies and strong communication skills are required. 

Ability to work with customers and R&D teams is important. Proficient with HDL (Verilog/VHDL), HVL(e/vera/systemverilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering. Experience on VMM/OVM/UVM and knowledge of simulator-emulator co-emulation are preferred.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.