Synopsys

• Job Responsibilities:
• Develop and execute validation plans for new feature of tools, developing testcases, build DFT flow (insertion, scan stitch, ATPG, simulation), debug, documentation.
• Collaborate with R&D teams to resolve tool defects and enhance tool capabilities.  
• Raise and track defects and enhance/add test suites to improve Quality of Product.
• Collaborate with domain experts to improve the Product quality.
• Consultation for test solutions during design planning/budgeting/implementing.
• Test methodology design rules checking during RTL coding stages.
• Implementation of design for test (DFT) compression, validation,  automatic test generation for single stuck at (SSAF), Transition Delay Fault, Cell-aware faults, and other advanced fault models.
• Participation in customer’s design and flow reviews.
• Diagnostics analysis and debug.
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• Job Requirement/Skills required:
• Strong knowledge of frontend digital design concepts, ASIC flows and EDA tools.
• Strong RTL design and coding experience in Verilog, system Verilog, VHDL etc.
• Working knowledge of scripting on unix- Perl/Python and TCL.
• Excellent teamwork, communication in English, interpersonal skills with team members.
• Desire to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
• Knowledge in Design for Test (DFT) technologies and concepts is an added advantage.
• Hands-on Experience with Synopsys DFT tool is a strong plus.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.