Synopsys

We are a team working on producing the highly optimized hardware IP for the ARC family of configurable processors. We are looking for an engineer like you to be part of the team to work on our world-class micro-processors that allow our customers to develop highly optimized and sophisticated embedded designs. 

Job Description: 

• To investigate the appropriate level to deploy the formal verification to various design modules (FIFO, arbitrator, coherency unit) with high efficiency 
• To investigate the cache/performance modeling to mimic popular and standard processor benchmarks in a multi-core processor 

Job Requirements: 

• Understanding of design languages such as, SystemVerilog, Verilog
• Knowledge of System C
• Knowledge of tools such as, RTL Simulators, e.g. VCS
• Knowledge of HDL design and ideally, computer architecture, RISC architectures, multi-core, etc.
• Good independent thinking and problem-solving skills
• Excellent written and verbal skills, including Written and spoken English, Detailed status reporting; Ability to present results to the program management teams
• Contagious enthusiasm and passion for engineering.
• A bachelor’s degree in engineering is a minimum requirement

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. 

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. 

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.