Synopsys

Job Title: DDR I/O Circuit Design Apprenticeship

Introduction:
We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Apprenticeship Experience: At Synopsys, Apprentice dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement: Our mission is to fuel today’s innovations and spark tomorrow’s creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond.

What You’ll Be Doing:

• Designing DDR I/O circuits and layouts for advanced semiconductor applications.
• Collaborating with internal development teams to ensure high-quality product outcomes.
• Applying knowledge of CMOS circuit design, layout methodology, and flow to assigned projects.
• Supporting the execution of circuit design tasks with a focus on efficiency and quality.
• Contributing to the understanding and implementation of JEDEC requirements for DDR interfaces and standards.

What You’ll Need:

• Recently completed a BE/BTech in Electrical & Electronics Engineering (EEE) or Electronics & Communication Engineering (ECE) from class of 2025.
• Knowledge of CMOS processes and deep submicron process technology challenges.
• Understanding of CMOS circuit design, layout methodology, and analog/mixed signal circuitry.
• Familiarity with basic ESD concepts is an advantage.
• Experience or coursework related to ASIC design flow.
• Knowledge of JEDEC requirements for DDR interfaces, DDR Timing, ODT, and SDRAM functionality is a plus.
• Ability to efficiently execute assigned circuit design tasks with attention to product quality.
• Strong written and verbal communication skills for effective teamwork.

Key Program Facts:

• Program Length: 12 months
• Location: Bengaluru, India
• Working Model: Onsite
• Full-Time/Part-Time: Full-Time
• Start Date: March 2026

Equal Opportunity Statement: