Synopsys

Seeking a motivated and innovative digital verification engineer with excellent theoretical and practical background in high-speed data recovery circuits. Candidate will be involved in verifying current and next generation SERDES products.

Responsibilities:

• Writing constrained-random System Verilog test benches using UVM and VMM.
• Writing new cover group and examine functional, assertions and code coverage.
• Defining and tracking verification test plans;
• Debugging RTL and gate-level simulations failures;
Candidates should have experience writing scripts in languages such as Perl, Python, Unix shell. 

Requirements:

Bachelor’s or Masters Degree in ECE/EEE

 

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.