Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation. You excel at collaborating with global teams, leveraging your deep understanding of circuit-layout interactions across various technology nodes to deliver robust solutions. Your knowledge spans the fundamentals of IC layout, foundry design rules, semiconductor device physics, and digital design, complemented by a strong foundation in CMOS technology.

With hands-on experience in advanced EDA tools and scripting languages such as Unix/Shell/Python/TCL/ICV, you’re eager to apply automation to streamline workflows and enhance productivity. You possess a keen eye for detail, ensuring every design meets stringent manufacturability, performance, and yield standards. Your problem-solving abilities, adaptability, and commitment to continuous learning make you an ideal candidate for this role. You embrace challenges, proactively seek feedback, and contribute to a culture of excellence and innovation. Whether working independently or within cross-functional teams, your communication skills and technical acumen ensure you are a valuable contributor to world-class IP solutions.

What You’ll Be Doing:

• Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.
• Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.
• Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.
• Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.
• Conducting design reviews and offering constructive feedback to enhance quality and performance.
• Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

The Impact You Will Have:

• Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.
• Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys’ IP products.
• Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.
• Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.
• Fostering collaboration across global teams, leading to improved methodologies and best practices.
• Maintaining the highest standards of quality, compliance, and performance in every design delivered.

What You’ll Need:

• BTech/MTech in Electrical Engineering, Electronics, or related field.
• 2+ years of relevant experience in IC layout design, preferably in standard cell libraries.
• Proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM).
• Hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs.
• Strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting.
• Solid understanding of sign-off flow, waiver handling, and quality tracking.
• Excellent written and spoken English for technical communication.
• Deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals.
• Ability to work independently and collaborate effectively across teams.

Who You Are:

• Analytical thinker with meticulous attention to detail.
• Enthusiastic collaborator, comfortable working in global, cross-functional teams.
• Proactive problem solver, adaptable to evolving technologies and methodologies.
• Effective communicator, able to articulate complex concepts and feedback clearly.
• Continuous learner, committed to professional growth and innovation.

The Team You’ll Be A Part Of:

You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization’s goals. Together, you’ll push the boundaries of semiconductor design, leveraging collective expertise to deliver industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.