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General Information

Job Title
Analog/Mixed-Signal Layout and Methodology Design Engineer
Job ID
4523
Country
India
City
Hyderabad
Date Posted
03-Sep-2024
Job Category
Engineering
Job Subcategory
Layout Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
Looking for innovative out of the box thinking Layout Engineer to be part of the Analog and Mixed Signal IP Methodology Team at Synopsys. In this role you will be responsible for developing and maintaining layout automation scripts to support the development of custom analog and digital blocks for multi-Gb/s SERDES IP.  Challenges include coming up with solutions to problems imposed by advanced technology nodes. A successful candidate will be expected to have a sound commitment to write efficient and stable scripts and keep up with advancements in IC design and methodology. As part of the Methodology team you will be exposed to SerDes PHY layout for PCIe, SATA, XAUI, and other protocols.   Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team. Responsibilities also include:
  • Providing quick solutions (usually TCL/Perl prototypes) to show that engines in design tools can be extended to meet internal requirements
  • Working closely with PDK and IC design tools team by effectively participating and influencing the technical strategy and execution to improve methodology
Requirements
  • BE/BTECH/MS in Electrical/Electronic Engineering, Computer Engineering, or related practice with 2 years’ experience in programming EDA software.
  • Strong knowledge required on layout matching technics, Shielding, EMIR, Antenna
  • Understanding capability to solve physical verification: DRC/LVS/ERC
  • Understanding of Linux and common scripting languages (BASH, CSH, Python, Perl, Tcl) are added advantage
  • Hands-on experience of working on high-performance cores and advanced node technologies (10nm, 7nm, 5nm,4nm)
  • Understanding of VLSI design flow and methodology.
  • Ability to be proactive and have a strategic mindset in addition to having tactical problem-solving experience
  • Prior understanding and experience of Synopsys EDA tool development would be a plus.
  • Effective written and oral communication skills
  • In depth familiarity with layout of analog and mixed signal CMOS circuits
  • Good understanding of how layout tools function and have had experience using them.
  • Solid desire to learn and explore new technologies.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.