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General Information

Job Title
Layout Design, Sr Supervisor
Job ID
5077
Country
India
City
Bangalore
Date Posted
03-Sep-2024
Job Category
Engineering
Job Subcategory
Layout Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
Job Description
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars, artificial intelligence, the cloud, 5G, IOT breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
 
Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world’s broadest portfolio of silicon IP -- predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

We are hiring visionary leaders for our next generation DDR/HBM/UCIe PHY IP’s!

Responsibilities:
  • Sr Supervisor to lead next generation DDR/HBM/UCIe IP development
  • Has leadership qualities to lead developments of new technologies while demonstrating good analysis and problem-solving skills
  • Acts as an advisor to employees to meet schedules and/or resolve problems
  • Perform in project leadership role and contributes to complex aspects of a project
  • Develop and maintain schedules, work in cross-functional settings while being proficient in layout & verification
  • You will be required to mentor junior resources while extracting the best out of senior ones.
  • Able to lead small layout team, understanding of PHY level constraints, effort estimation and schedule planning, project execution
  • Work with team to support critical layout, floorplanning requirements, layout reviews and quality checking
  • Provide subject matter expertise & technical leadership in high-speed DDR/HBM/UCIe IP layout
 
Requirements
  • Qualification: BTech/MTech
  • Skills/Experience: 8+ years relevant and team managing experience
  • Ability to lead projects with best product quality and efficiency. Cross collaboration with teams, coordination and high-quality layout execution, foster accountability and ownership through hands-on technical leadership.
  • In-depth understanding of deep submicron effects, floorplan techniques in CMOS, FinFET, GAA process technologies 7nm and below
  • Efficiency in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements
  • Scripting skills for layout automation is a plus
  • Good written and verbal communication skills in interactions to lead development teams

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.