Synopsys

Alternate Job Titles:

• Staff Layout Engineer – DDR/HBM PHY IP

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk. We’re building the next generation of DDR & HBM PHY IPs—come be a part of this cutting-edge journey.

You Are:

You are a passionate and innovative Staff Engineer who thrives on turning complex technical challenges into industry-leading solutions. You have deep expertise in physical layout design, especially within advanced process nodes (7nm and below), and a proven history of hands-on project leadership in high-performance IP development. Your curiosity drives you to stay at the forefront of technology, and your collaborative spirit enables you to mentor and empower junior engineers while working seamlessly within cross-functional teams. You are adept at balancing technical rigor with practical execution, ensuring that projects adhere to the highest standards of quality, reliability, and efficiency.

You embrace diversity and foster inclusion, valuing different perspectives and backgrounds to drive innovative thinking. Your communication skills—both verbal and written—allow you to articulate complex technical concepts with clarity and influence stakeholders at all levels. You are committed to continuous learning, actively seeking opportunities to expand your knowledge in areas like deep submicron effects, advanced floorplanning, and best practices in ESD, PERC, and DFM. Above all, you are a proactive problem solver, ready to lead, mentor, and make a tangible impact in a dynamic, fast-paced environment.

What You’ll Be Doing:

• Leading the design and development of next-generation DDR and HBM PHY IP layout, driving technical innovation and best practices.
• Providing technical mentorship and guidance to junior engineers, fostering skill development and knowledge sharing across the team.
• Taking ownership of layout planning, execution, and quality review processes to ensure on-time delivery of high-quality silicon IP.
• Collaborating with cross-functional teams—including circuit design, verification, and product engineering—to meet project goals and customer requirements.
• Managing effort estimation, project scheduling, and execution in multi-disciplinary team settings.
• Reviewing and optimizing layout for advanced process technologies (CMOS, FinFET, GAA), ensuring compliance with DFM, EMIR, and reliability standards.
• Supporting critical phases such as floorplanning, LEF generation, bond-pad layout, IO frame and pitch requirements, and release processes.

The Impact You Will Have:

• Accelerating the delivery of industry-leading DDR and HBM PHY IP to global customers, enabling their next-gen products.
• Driving technical excellence in layout design, setting new benchmarks for quality, reliability, and performance.
• Mentoring and upskilling junior team members, contributing to a strong, knowledge-driven team culture.
• Ensuring that Synopsys’ IP solutions meet and exceed evolving market demands for power, performance, and area (PPA).
• Reducing customer risk and time-to-market by delivering robust, silicon-proven IP solutions on schedule.
• Enhancing Synopsys’ reputation as a leader in Silicon IP, contributing to customer satisfaction and long-term business growth.

What You’ll Need:

• BTech/MTech degree in Electronics, Electrical Engineering, or a related field.
• Minimum 5 years of relevant experience in physical layout design, particularly in advanced nodes (7nm and below).
• Strong command of deep submicron effects, advanced floorplan techniques, and process technologies such as CMOS, FinFET, and GAA.
• Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and bond-pad/IO frame design.
• Demonstrated ability to lead projects, manage schedules, and deliver high-quality results within tight timelines.
• Proficiency in using industry-standard EDA tools for layout and verification.

Who You Are:

• Innovative and proactive, with a growth mindset and strong problem-solving skills.
• Effective communicator, able to convey technical information clearly to diverse audiences.
• Collaborative team player who values accountability, ownership, and inclusivity.
• Mentor and motivator, enthusiastic about supporting the growth and success of others.
• Flexible and adaptable, thriving in a dynamic, fast-paced environment.

The Team You’ll Be A Part Of:

You will join a world-class Silicon IP team dedicated to pushing the boundaries of high-performance memory interface design. Our team thrives on innovation, technical excellence, and a collaborative spirit. We work closely with experts from circuit design, verification, product engineering, and customer support to deliver differentiated IP solutions that power the world’s most advanced SoCs. Together, we foster a culture of continuous learning, mentorship, and mutual respect—where every member’s contribution drives our collective success.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.