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General Information

Job Title
Layout Design, Staff Engineer
Job ID
7001
Country
Portugal
City
Porto Salvo
Date Posted
15-Oct-2024
Job Category
Engineering
Job Subcategory
Layout Design
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements
We’re looking for a Layout Design Engineer to join our team. On this role you’ll acquire and develop competences in all layout design activities, ranged from layout entry, floor planning verification and quality validations. The focus of our team is developing high speed SerDes physical interface and design all the necessary analog blocks to support it ranging from basic blocks to complex structures that touch the boundary of chip interface. 


Key Qualifications:
  • MSc in Electrical or Computer Engineering (or equivalent) with background on transistor level and 4+ years working experience in layout circuit design;
  • Good knowledge in deep submicron CMOS technologies;
  • Good judgment in selecting efficient/robust methods and techniques to layout floorplan and validation;
  • Design for porting (i.e. design to enable ease moving layout across multiple foundry nodes);
  • Knowledge of signal integrity issues and techniques to mitigate ESD, latchup (i.e. clock/data routes, differential routing, shielding, well distance, substrate biasing);
  • Familiarity with custom digital layout (i.e. high speed digital paths);
  • Knowledge of layout effects and design for reliability (i.e. matching, reliability, proximity effects, EM, IR, etc.);
  • Ability to build productive internal/external working relationships. Networks with senior internal and external personnel in own area of expertise;
  • Familiarity with UNIX operating systems and IC design tools;
  • Good written and verbal English language skills.

Required Experience:
  • Familiarity with layout of analog and mixed signal CMOS circuits;
  • Contribution to the development of complex layout integrated circuits;
  • Knowledgeable about signal integrity (ie. clock/data routes, differential routing, shielding);
  • Implementation of ESD design constraints, latch-up risk mitigation;
  • Layout design for reliability (ie. EM, IR, etc…);
  • Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects, etc…).

Preferred Experience
  • Knowledge on Synopsys EDA tools;
  • Familiar with Unix and scripting languages (TCL, Python);

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned digital blocks, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.


Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.