Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and detail-oriented layout design professional with a passion for precision and quality. You thrive in environments where you can take full ownership of complex custom layout tasks, from initial floorplanning through to post-layout closure. Your expertise in analog and mixed-signal layout fundamentals—such as device matching, common-centroid, interdigitation, symmetry, guard rings, and shielding—sets you apart. You are driven by the challenge of optimizing layouts for parasitics, reliability, and manufacturability, and you have a proven track record of closing designs that meet or exceed demanding circuit metrics.
 
 You understand the importance of adherence to foundry and PDK rules, and you are vigilant in tracking waivers and risk areas early in the design process. Your fluency with industry-standard tools like Custom Compiler, ICV Workbench, and Calibre—along with comfort scripting in SKILL—enables you to work efficiently and automate recurring tasks. As a staff-level engineer, you demonstrate leadership by setting clear schedules, proactively identifying risks, and ensuring high-quality deliverables. You are a collaborative team player who aligns cross-functional stakeholders, raises the bar for layout standards, and coaches colleagues to scale team capability. Your communication skills are top-notch: you provide concise updates, clarify trade-offs, and ensure no surprises at tape-in milestones. You are energized by the opportunity to contribute to a culture of continuous improvement and innovation.

What You’ll Be Doing:

• Owning end-to-end custom layout for complex analog and mixed-signal blocks, from floorplan through routing and post-layout closure.
• Applying advanced analog layout techniques, including common-centroid, interdigitation, symmetry, guard rings, shielding, and sensitive-net routing.
• Driving parasitic-aware layout and closure, considering PEX, coupling, IR/EM, and PERC to optimize circuit performance and reliability.
• Ensuring full signoff discipline by efficiently debugging DRC, LVS, ANT, PEX, and PERC violations and tracking closure progress.
• Interpreting foundry and PDK rules, managing waivers, anticipating risks, and ensuring compliance throughout the design process.
• Leading cross-team alignment with design, verification, CAD/methodology, and signoff stakeholders to achieve project milestones.
• Establishing and maintaining high standards by creating guidelines, checklists, reusable templates, and automation to minimize recurring errors.
• Coaching and mentoring junior layout engineers, providing clear feedback and teaching points during layout reviews.

The Impact You Will Have:

• Delivering high-quality, tape-in-ready layouts that are critical for the success of Synopsys’ leading-edge silicon solutions.
• Enhancing product performance, yield, and reliability through meticulous layout optimization and adherence to best practices.
• Reducing time-to-market by proactively identifying and mitigating risks, ensuring smooth signoff and closure processes.
• Raising the technical bar by developing and sharing standards, guidelines, and automation tools across the team.
• Fostering a culture of collaboration and knowledge sharing by coaching and mentoring peers and less experienced engineers.
• Driving continuous improvement in layout methodologies, contributing directly to Synopsys’ reputation for innovation and excellence.

What You’ll Need:

• 5-8 years of layout design experience.
• Expertise in end-to-end custom analog/mixed-signal layout, including floorplanning, routing, and post-layout closure.
• Deep understanding of device matching, common-centroid, interdigitation, symmetry, guard rings, shielding, and sensitive-net routing.
• Proficiency in parasitic-aware layout with a strong grasp of PEX, coupling, IR/EM effects, PERC, and their impact on circuit metrics.
• Hands-on experience with DRC, LVS, ANT, PEX, and PERC signoff, including efficient debugging and closure discipline.
• Solid knowledge of foundry/PDK rules, ability to interpret and track waivers, and anticipate risk areas early in the process.
• Fluency with layout tools such as Custom Compiler, ICV Workbench, Calibre, and scripting (SKILL or similar) for automation.
• Understanding of DFM and reliability basics relevant to the design node (latch-up, ESD, antenna, density/fill interactions).

Who You Are:

• A proactive problem solver who takes ownership of schedule, quality, and risk management for layout blocks.
• A collaborative leader who aligns with design, verification, CAD, and signoff teams to achieve shared goals.
• An advocate for high standards, always seeking to improve processes, guidelines, and team capability.
• An effective communicator, delivering concise status updates, clear trade-offs, and ensuring transparency at milestones.
• A mentor and coach who shares knowledge and scales expertise across the team.
• Adaptable, detail-oriented, and driven by a passion for continuous learning and innovation.

The Team You’ll Be A Part Of:

You’ll join a world-class custom layout team at Synopsys Armenia, collaborating with experts in analog/mixed-signal design, verification, CAD methodology, and signoff. The team is dedicated to developing cutting-edge silicon solutions, fostering a culture of technical excellence, collaboration, and innovation. You’ll have the opportunity to lead, mentor, and help shape industry-leading layout practices that make a difference at a global scale.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.