Synopsys

• Design and development of transistor to macro level analog and mixed signal layout.
• Device level floorplan, placement, routing, and physical verification.
• Troubleshoot Physical verification issues to get clean and desired results.
• In charge of creating and reviewing layout documents to ensure they meet quality standards and are delivered on time.

• Candidate must have a bachelor's or master's degree and a minimum 5 years of experience in Analog and Mixed Signal Circuit Layout.
• Experience in Analog Layout Flow from Device placement till GDS release.
• Should be able to do planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
• Sound knowledge in Electrical and Electronic fundamentals.
• Solid Knowledge in Semiconductor device physics, good knowledge of CMOS, FINFET technologies.
• Knowledge of CMOS Fabrication technology and deep sub-micron effects and its impact on layout.
• Must know the Electro migration and other Reliability Concepts, ESD/LUP concepts and apply to layout.
• Hands on knowledge in EDA tools for Custom Mixed signal layout flows.
• Passionate to learn and explore new techniques.
• Must be self-directed, detail oriented with good problem-solving skills and communication skills.
• Effectively communicating with cross-functional team for successful project execution.
• Experience in Tcl is a plus.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.