Synopsys

Alternate Job Titles:

• Senior Layout Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

As a Layout Design, Sr Engineer, you are a highly skilled professional with a passion for technology and innovation. You thrive in a collaborative environment and are driven by the challenge of developing cutting-edge technologies. Your expertise in layout development for next-generation DDR/HBM/UCIe IPs is complemented by your problem-solving abilities and attention to detail. You have a solid understanding of deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies at 7nm and below. Your experience with layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation ensures you can meet quality requirements and timelines efficiently. You are an excellent communicator, both in writing and verbally, and possess strong interpersonal skills that foster collaboration and accountability within your team.

What You’ll Be Doing:

• Developing layouts for cutting-edge technologies in next-generation DDR/HBM/UCIe IPs.
• Solving complex problems and debugging layout issues.
• Working on layout floorplans, routing, and physical verifications to ensure quality.
• Meeting timelines and verification requirements such as DRC, LVS, ERC, and Antenna.
• Collaborating with cross-functional teams to achieve project goals.
• Continuously improving layout techniques and processes.

The Impact You Will Have:

• Contributing to the development of high-performance silicon IPs.
• Ensuring the reliability and functionality of Synopsys products.
• Enhancing the capabilities of SoC integration with advanced layout designs.
• Reducing time-to-market for differentiated products.
• Minimizing risks associated with layout development through rigorous verification.
• Supporting the continuous innovation and technological advancement of Synopsys.

What You’ll Need:

• BTech/MTech degree in a relevant field.
• 5+ years of experience in layout development and verification.
• Proficiency in DRC, LVS, ERC, and Antenna verification techniques.
• Strong understanding of CMOS, FinFET, and GAA process technologies at 7nm and below.
• Experience with layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

Who You Are:

• Detail-oriented with excellent problem-solving skills.
• Effective communicator with strong interpersonal abilities.
• Collaborative team player who fosters accountability and ownership.
• Adaptable and open to continuous learning and improvement.
• Passionate about technology and innovation.

The Team You’ll Be A Part Of:

You will join a dynamic team of engineers dedicated to developing next-generation DDR/HBM/UCIe PHY IPs. Our team is committed to pushing the boundaries of technology and delivering high-quality, reliable silicon IPs. We work collaboratively, sharing knowledge and expertise to achieve common goals and drive innovation in the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.