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General Information

Job Title
Standard Cell Design Lead
Job ID
7165
Country
Taiwan
City
Hsinchu
Date Posted
27-Oct-2024
Job Category
Engineering
Job Subcategory
R&D Engineering
Hire Type
Employee
Remote Eligible
No

Descriptions & Requirements

Job Description and Requirements

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a dedicated and experienced Standard Cell Library Design Engineer with a passion for cutting-edge technology and innovation. You possess a strong background in designing and optimizing standard cell circuits, including flip-flops, clock gating cells, level shifters, power gating cells, and other complex circuits in advanced technology nodes. Your expertise in circuit design, layout design, and spice simulations allows you to excel in creating high-performance, power-efficient circuits. You thrive in collaborative environments, working effectively with geographically distributed teams and engaging in cross-functional collaborations to optimize designs across the entire design chain. Your strong analytical and logical skills, combined with your ability to mentor and coach junior engineers, make you an invaluable asset to any team. With a clear understanding of CMOS device characteristics, submicron process issues, and FINFET technologies, you are well-equipped to tackle the challenges of advanced technology nodes. Your scripting capabilities in TCL, PERL, and Python further enhance your ability to optimize and automate design processes.

What You’ll Be Doing:

  • Designing and optimizing standard cell circuits such as flip-flops, clock gating cells, level shifters, power gating cells, and other complex circuits in advanced technology nodes.
  • Engaging in cross-functional collaborations for optimization across the entire design chain.
  • Working closely with geographically distributed teams to achieve design PPA targets.
  • Mentoring and coaching junior engineers to expand their skills.
  • Conducting hands-on development and layout design.
  • Running high sigma variation analysis in smaller technology nodes.

The Impact You Will Have:

  • Contributing to the development of high-performance, power-efficient circuits that drive the next generation of technology.
  • Enhancing the performance, power, and area (PPA) of standard cell libraries.
  • Facilitating cross-functional collaborations to optimize designs across the entire design chain.
  • Mentoring and developing the next generation of engineers.
  • Ensuring the success of projects through effective communication and collaboration with geographically distributed teams.
  • Driving innovation in advanced technology nodes and submicron processes.

What You’ll Need:

  • Bachelors or MSEE or equivalent from reputed universities.
  • At least 10 years of Standard Cell library design & layout experience.
  • Hands-on experience in Circuit Design, Layout Design & spice simulations.
  • Experience in designing flip-flops, clock gating cells, level shifters, power gating cells, and other complex circuits.
  • Familiarity with advanced technology nodes (16nm, 7nm, 6nm, 5nm, 4nm, 3nm, 2nm).
  • Clear understanding of CMOS device characteristics and design rules in submicron process nodes.
  • Scripting capability in TCL/PERL/Python.

Who You Are:

  • Strong analytical and logical skills.
  • Effective communicator with the ability to articulate ideas and requests clearly.
  • Collaborative team player who thrives in cross-functional environments.
  • Mentor and coach who supports the development of junior engineers.
  • Innovative thinker with a passion for cutting-edge technology.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on the design and optimization of standard cell libraries. This team collaborates closely with other R&D teams across the globe to achieve design PPA targets and drive technological advancements in advanced technology nodes. As a member of this team, you will have the opportunity to work on cutting-edge projects and contribute to the development of next-generation semiconductor technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.