Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned professional with a passion for RTL Design and Verification. With 4-9 years of experience in electronics, you possess a deep understanding of RTL Signoff Checks such as LINT, CDC, and RDC. You thrive in dynamic environments and are adept at developing timing constraints for synthesis and timing. Your hands-on experience with static verification tools, including Spyglass, positions you as an expert in your field. You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings. Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched. You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs. If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you.

What You’ll Be Doing:

• Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC.
• Understand design/architecture and develop timing constraints for synthesis and timing.
• Run preliminary synthesis to ensure design can be synthesized as intended.
• Run formality to ensure equivalence of RTL and gates.
• Integrate IPs in SoCs/Subsystems and create RTL design as per customer needs.
• Collaborate with cross-functional teams to deliver high-quality RTL designs.

The Impact You Will Have:

• Ensure high-quality RTL Signoff for semiconductor designs.
• Contribute to the development of cutting-edge semiconductor technologies.
• Improve design efficiency and performance through effective timing constraints.
• Enhance the reliability and functionality of SoCs and subsystems.
• Support customer success by delivering tailored RTL designs.
• Drive innovation in RTL Design and Verification methodologies.

What You’ll Need:

• B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years’ experience in RTL Design and Verification.
• Hands-on experience with static verification tools such as Spyglass performing LINT, CDC, RDC.
• Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossings.
• Strong grasp of RTL rule checks.
• Proficiency in synthesis and timing constraints development.

Who You Are:

• Detail-oriented with a focus on quality and precision.
• Excellent problem-solving skills and analytical thinking.
• Strong communicator, able to collaborate effectively with cross-functional teams.
• Adaptable and open to learning new technologies and methodologies.
• Proactive and self-motivated, with a passion for innovation.

The Team You’ll Be A Part Of:

The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.