Synopsys

Job Description Summary the PLL Analog-mixed signal group designs/maintains (and verify) physical layer PLLs for high-speed wireline data communication, for different protocols in MAC (mobile, automotive, consumer) market.

• BS EE/MSc (preferred) in the areas of high-performance analog/mixed-signal design and verification principles.
• Understanding ofanalog and mixed-signal circuit design and verification principles.
• Solid experience with EDA tools such asSynopsysCustom Compiler,hspiceand AMS simulators.
• Understanding of fundamentals, including:
• Transistorleveldesign.
• PLL loop design.
• High precision analog circuits (including linear regulators,bandgapreferences,current source, Analog Filters)
• programmingskills,can write efficient programs or scripts in Python, Verilog/Verilog-A is a plus.

Additional Job Description

• Own verificationandmaintenanceof major blocks or entirePLL.
• Develop and implement mixed signal verification plans forPLLsbased on design architecture and specifications.
• Design and develop verificationtest benchesusing industry-standard verification languages and methodologies.
• Review and analyze verification results and provide feedback to design teams.
• Maintain detailed documentation of verification plans, test results, and designchanges(MS Office skillsrequired).

• Collaborate with design and layout teams toidentifyand resolve design issues.
• Work withvarious technologies and process nodes.