Synopsys

We are looking for an experienced Memory Layout Engineer to join our custom memory design team. In this role, candidate will be responsible for the physical layout implementation SRAM memory macros in advanced semiconductor technology nodes. Candidate will work closely with circuit designers, physical design engineers, and process teams.

Key Responsibilities:

               Develop full-custom layout for SRAM memory 

Create highly optimized layouts

Perform and resolve DRC/LVS/ERC/Antenna/Density and EM checks

Collaborate with circuit and architecture teams

Required Qualifications:

Bachelor’s or Master’s degree in:

 Electrical Engineering
 Electronics Engineering
 Microelectronics
 1+ years of hands-on experience in SRAM/custom memory layout design.

Strong expertise in:

 SRAM architecture and memory circuits
 Custom layout techniques
 Matching and symmetry
 Device reliability and variation effects
 Experience with advanced technology nodes

Proficiency with industry-standard EDA tools including:

Cadence Virtuoso
 Calibre
 Custom Compiler

ICV

Strong understanding of:

 DRC/LVS closure
 RC extraction
 EM/IR considerations

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.