Synopsys

You Are

You have built a solid foundation in physical verification and you know that clean signoff is what separates a successful tapeout from a costly respin. You have spent enough time in the ASIC flow to understand how floorplanning decisions ripple through to DRC violations, and you care about catching those issues early rather than at the last minute.

You are comfortable working with GDS databases, running LVS checks, and debugging failures that require you to trace back through multiple stages of the design. You do not need someone to hold your hand through every verification run, but you are smart enough to ask questions when something does not make sense. You write scripts because you know that automating repetitive tasks makes everyone's life easier, including your own.

You work well with others. Implementation teams, CAD engineers, design leads, you understand that getting to tapeout requires collaboration, not just technical skill. At Synopsys, you will work on real chip designs alongside an experienced SoC team, and what you verify will directly impact whether silicon works when it comes back from the fab.

What You'll Be Doing

• Run block level physical verification including DRC, LVS, and DFM checks to ensure designs meet foundry requirements
• Build and verify final GDS, OASIS, and DEF databases for tapeout readiness
• Develop and validate ICV verification flows and methodologies working with the CAD team
• Perform routability analysis during floorplanning to identify potential congestion issues
• Work with implementation teams throughout the chip design cycle to close signoff issues before tapeout deadlines
• Debug physical verification failures and work cross-functionally to resolve them

The Impact You Will Have

• Your verification work ensures chips tapeout clean, avoiding costly respins and schedule delays
• The flows you build will be reused across multiple projects, improving efficiency for the entire team
• Your collaboration with implementation and CAD teams will help catch design issues earlier in the flow
• You will contribute to chips that power real products in AI, automotive, and consumer electronics
• Your attention to detail at signoff directly affects whether silicon works on first pass
• The methodologies you help validate will become part of how Synopsys approaches physical verification

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering with 3+ years of physical design and signoff verification experience
• Strong understanding of ASIC development flow, digital design, physical implementation, and signoff verification
• Hands-on experience with floorplanning, block integration, place and route, and physical verification
• Working knowledge of physical PDV, DRC/LVS verification, and DFM
• Scripting experience in Python, Tcl, or Perl
• Experience with test chip or full chip verification is a plus

Who You Are

• You can debug a DRC violation by tracing it back through the layout and figuring out what actually caused it
• You write scripts that get the job done and are clear enough that someone else can use them later
• You speak up when you see a potential issue in the design flow rather than waiting for it to become a problem at signoff
• You stay organized when managing multiple verification runs and can prioritize what needs attention first
• You build good working relationships with implementation and CAD teams because you know verification does not happen in a vacuum

The Team You'll Be Part Of

You will work with a highly experienced digital and mixed-signal SoC team focused on building high-performance silicon chips. You will collaborate directly with implementation engineers and CAD teams throughout the chip design cycle, contributing to real production tapeouts. The team values quality, ownership, and continuous improvement.

#TPG

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.