Synopsys

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a dynamic engineer with working experience in RTL implementation, verification, flow automation with TCL and understanding of DDR PHY protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you a valuable asset to any team. You excel in communication, teamwork, and multitasking, and have experience working in cross-functional, multi-site environments.

What You’ll Be Doing:

• Working closely with a world-class R&D team,you’llbe at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM).
• Working closely with customers, you will bring the detailed requirements into the factory to enable R&D fora strong, robust, and successful product development.
• Working closely withproductdevelopment team, you willvalidateandend-to-end solution both internally (before shipment) as well as incustomerenvironment.
• Driving the deployment and smooth execution of SLM solutions into customers’ projects.
• Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The Impact You Will Have:

• EnhancingSynopsys’ Silicon Lifecycle Management (SLM) IPportfolio and end-to-end solutionespecially inthe growing field of multi-die domain.
• Driving the adoption ofSynopsys’ SLM solutions at premier customer baseworldwide.
• Influencing the development of next-generationSLM IPs and solutions.

What You’ll Need:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
• 8+ years ofhands-on experience with RTLandGateleveldesign and verificationinvolvingMBIST, JTAG & iJTAG.
• Strong understanding ofMBIST.
• Good exposure toJTAGIEEE 1149.1, IEEE 1687/1500,Testdata access mechanism.
• Functional verification around anyDDR/PCIe/USBorany otherprotocol knowledge is a plus.

• Exposure to other DFT methodologies like SCAN is a plus.
• Debugging abilities to identifyandresolveissues.
• Hands on experienceinflow automation using TCL(Python knowledge is a plus).
• Knowledge of Synthesis is a must with understanding of timing constraints (SDC).
• Knowledge of Lint, CDC, RDCis a plus.
• Knowledge of physical implementation is not a must, but good to have.
• Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions
• Customer facing experience is a plus – educating/guiding customer on technical details of a solution 
• Good to have: 
• Hands-onbring-up anddebug experience of silicon is a plus
• Architecture/micro-architecture experience

The Team You’ll Be A Part Of:

As part of the Silicon Lifecycle Management (SLM) solutions team, you will collaborate with global R&D teams to develop world-class IPs and end-to-end solutions to address silicon health issues at premier data center, AI, and automotive customers. Our team is dedicated to bringing solutions to enhance the life of a silicon anywhere it belongs.